Stress engineering plays an important role in increasing the performance of semiconductor devices. Typical examples of such application of stress are widely used strained semiconductor lasers and strained transistors (e.g., strained-channel field effect transistors, FETs) and related strained circuits such as complementary metal oxide semiconductor (CMOS) circuits. In the case of strained FET channels, the stress is applied to the transistor structure in such a way that the device channel region is beneficially strained causing increased mobility of electrons (or holes), which in turn gives a substantial improvement in device speed. The positive effect of crystal lattice strain onto electron and hole mobility depends on the crystal symmetry of a particular semiconductor and how various components of the strain tensor in the transistor channel are related to the semiconductor lattice symmetry or, more specifically, how they are related to the symmetric planes, axes, and centers of symmetry of the lattice.
Accordingly, the type of beneficial channel strain is a strong function of (a) semiconductor type; (b) carrier type (electron or hole); (c) crystal orientation and rotation of the channel plane; and (d) direction of electrical current in the channel. Further, the beneficial channel strain can be induced by many different techniques because it depends on the transistor's geometrical structure and how the external stress is applied.
In one useful example, the stress is applied to both silicon-based nFETs and pFETs formed on standard (100) silicon wafers via a highly stressed film that covers the transistor gates and partly covers the source/drain regions. This type of highly stressed film is referred to in the art as a stressed gate liner. In such an application, a tensile stress gate liner is applied to the nFET device to improve electron mobility, while a compressive stress gate liner has been shown to speed up pFET devices. This situation is shown in FIG. 1.
Specifically, FIG. 1 shows (through a cross sectional view) a semiconductor structure 100 that comprises a semiconductor substrate 102 that includes an nFET device region 104 and a pFET device region 106 that are separated by an isolation region 108. Atop the nFET device region 104 is an nFET 120 that includes a gate dielectric 122 and a gate conductor 124 that is doped with an n-type dopant. The nFET 120 includes source/drain diffusion regions 126 that are located in the semiconductor substrate 102 and a spacer 121 that is located on exposed sidewalls of at least the gate conductor 124. The pFET device region 106 includes a pFET 128 that includes a gate dielectric 122 and a gate conductor 124 that is doped with a p-type dopant. Source/drain diffusion regions 126 for the pFET 128 are present in the semiconductor substrate 102 at the footprint of the pFET 128 and a spacer 121 is also present on exposed sidewalls of at least the gate conductor 124. As shown, a tensile nitride liner 130 is present in the nFET device region 104, while a compressive nitride liner 132 is present in the pFET device region 106.
In this prior art example, the stressed liner (represented by liner 130 and 132) is a stressor material which exerts a force on the transistor structure. Both the shape of the stressor (in this example, the liner which is self-aligned to the transistor channel), the type of its stress (tensile or compressive), and transistor structure yield a beneficial strain in the respective transistor channels 125. Once the crystal type and geometries of the transistor and stressor are fixed, a high level of stress in the stressor leads to a higher strain in the channel 125 resulting in a higher performance improvement. Accordingly, it is highly desirable to increase stress levels in a stressor material.
Other types of stressor materials are also known in the prior art. For example, a SiGe crystal island embedded into a silicon crystal can cause a highly compressive stress in surrounding Si. This crystalline stressor can be employed to improve performance of a Si-based pFET. In another example, an amorphous silicon nitride stressor is shaped in the form of a gate spacer.
Combinations of various types and shapes of stressors are also known to further improve device performance. For instance, the aforementioned embedded SiGe crystalline stressor can be combined with the aforementioned amorphous stressed gate liner to further improve performance of a Si-based pFET.
Despite the advances made in the prior art for forming amorphous stressed gate liners, there is a need for providing improved amorphous stressor materials wherein the stress level for both cases of tensile and compressive strain are increased. Such a material would be employed to increase the beneficial level of strain in the adjacent semiconductor structure, irrespective of the particular stressor shape, type of semiconductor crystal, type of semiconductor device, and geometry of the device.
Further, it highly desirable that the improved stressor material is formed at a low temperature (on the order of about 400-550° C. or below) so as to preserve temperature-sensitive elements of the adjacent microstructure. For example, certain III-V compound semiconductors such as, for example, GaAs, are not stable above 500° C. In addition, certain elements of silicon-based transistors (e.g., the silicide contacts and the highly-activated dopants) can be undesirably affected by high-temperature processes.
Plasma-enhanced chemical vapor deposition (PECVD) processes are conducted at below about 500° C. One well-known example of an amorphous stressor material is an amorphous silicon nitride film deposited by a PECVD process. Typically, the stress in silicon nitride films formed by PECVD is modulated by optimizing gas flows, plasma powers and other deposition parameters. Such optimization only provides modest gains in stress level, while it is very effective in adjusting the stress sign (compressive or tensile).
It is also possible to achieve relatively high stress level in SiN thin films by increasing the PECVD deposition temperature (above 500° C.) or by using a high temperature rapid thermal chemical vapor deposition (RT CVD) technique at a temperature of about 600° C. or above. While RT CVD can produce highly strained tensile SiN films, the typical temperature of the RT CVD process is close to 700° C.
Also, compressive RT CVD films are not known to exist. State of the art CMOS devices have relatively low middle-of-the-line (MOL) temperature budget, which is gradually approaching the back-end-of-the-line (BEOL) temperatures of about 400° C. The MOL temperature budget issue is becoming especially acute for devices based on high-temperature-unstable NiSi since defect levels in these devices increase dramatically with a temperature greater than 450° C. Therefore all high temperature MOL solutions cannot be used and achieving a high stress level by a PECVD technique at low temperature (less than 450° C.) is becoming a critical component of 65 and 45 nm node device engineering.